Processed Substrate

ABSTRACT

Representative implementations of techniques, methods, and formulary provide repairs to processed semiconductor substrates, and associated devices, due to erosion or “dishing” of a surface of the substrates. The substrate surface is etched until a preselected portion of one or more embedded interconnect devices protrudes above the surface of the substrate. The interconnect devices are wet etched with a selective etchant, according to a formulary, for a preselected period of time or until the interconnect devices have a preselected height relative to the surface of the substrate. The formulary includes one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.

PRIORITY CLAIM AND CROSS-REFERENCE TO RELATED APPLICATION

This application claims the benefit under 35 U.S.C. § 119(e)(1) of U.S. Provisional Application No. 62/439,746, filed Dec. 28, 2016, and U.S. Provisional Application No. 62/439,762, filed Dec. 28, 2016, which is hereby incorporated by reference in its entirety.

FIELD

The following description relates to processing of integrated circuits (“ICs”). More particularly, the following description relates to techniques for processing substrates.

BACKGROUND

Semiconductor chips are fabricated on suitable flat substrate wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon wafers, etc. After making the active devices, a series of steps are performed to connect the various devices using highly conducting wiring structures, so that the devices can communicate with each other to perform logic or memory storage operations, for example. The conductive wiring structures or interconnect structures are essentially a network of conducting materials, typically metals, in a matrix of dielectric materials. Conductive pads or terminals are coupled to the network of conducting materials, and are available at one or more locations at a surface of the substrate. With high performance devices, and to improve device density and yield, it is desirable to minimize topographic features within the interconnect layers for a given device and across the entire substrate. One common method of forming these high performance interconnect layers is the damascene process.

Multiple types of damascene structures are known, however single and dual damascene processes are the most common. In a single damascene process, each metal or via layer is fabricated in a series of operations, while in a dual damascene process, a metal layer and a via layer are fabricated in a similar operation. Of these two processes, the dual damascene technique is often preferred because of lower cost and higher device performance.

In the dual damascene process, a suitable substrate with or without devices is coated with a first suitable resist layer. The resist layer is imaged to define desirable patterns by lithographic methods on the substrate. Cavities are etched on the patterned substrates typically by reactive ion etching (RIE) methods. A second suitable resist layer is coated and patterned over the patterned dielectric layer in such a manner that the width of the first pattern is different from the width of the second pattern. The patterned substrate is then coated with a suitable barrier/seed layer prior to overfilling the cavities with a suitable metal, typically copper, by electro-deposition from a superfilling plating bath chemistry, for example.

The damascene process is repeated to form the many layers of interconnect. The substrate surface is polished after the final layer has been deposited. As a result of discontinuity in the properties (difference in mechanical properties, polishing rates, etc.) of the metal and insulator present on the substrate surface, and their respective interactions with the polishing pad, polishing slurry, and other process parameters, the polishing process often produces erosion in high metal pattern density features and dishing in large metal structures. Generally, the higher the metal pattern density, the higher the erosion in the dielectric layer of the substrate surface. Similarly, the larger the size of the metal cavity, the worse the gravity of the dishing defects. These deleterious defects can cause shorting defects in subsequent levels, reducing device yield.

Similar results are observed in cross section topographic profiles of polished through silicon via (TSV) structures. The centers of the vias are typically lower than the surface of the insulators, due to the dishing effects described.

One of the consequences of substrate surface dishing is poor flatness of the surface of the surface of the substrate and its interconnects. This can cause much higher pressures to be needed for bonding devices together or for wafer to wafer bonding, using so called hybrid bonding techniques. For example, dies and/or wafers may be bonded in a stacked arrangement using various bonding techniques, including direct bonding, non-adhesive techniques such as a ZiBond® technique or a hybrid bonding technique, also known as DBI®, both available from Ziptronix, Inc., a Xperi company (see for example, U.S. Pat. Nos. 6,864,585 and 7,485,968, which are incorporated herein in their entirety). These bonding techniques, and other similar techniques, require extremely flat bonding surfaces for the most reliable and the best performing bonds.

One method used to improve wafer to wafer bonding is to selectively recess the dielectric layer, so that the copper structures are protruding above the insulator surface prior to the bonding operation. This operation adds additional cost to the technology and is a source of defect when not properly implemented. Also, the poor flatness on the conductor surface often produces defective bonds, when the said surface is bonded or attached to other devices or substrates.

Other attempts to reduce the impact of these defects have included the incorporation of dummy dielectric features within large copper structures in dual damascene features for chip interconnects. This approach has been helpful, but it has also increased mask design complexity and the associated loss of freedom of structure placement on the modified pads.

BRIEF DESCRIPTION OF THE DRAWINGS

The detailed description is set forth with reference to the accompanying figures. In the figures, the left-most digit(s) of a reference number identifies the figure in which the reference number first appears. The use of the same reference numbers in different figures indicates similar or identical items.

For this discussion, the devices and systems illustrated in the figures are shown as having a multiplicity of components. Various implementations of devices and/or systems, as described herein, may include fewer components and remain within the scope of the disclosure. Alternately, other implementations of devices and/or systems may include additional components, or various combinations of the described components, and remain within the scope of the disclosure.

FIG. 1 is a schematically illustrated block diagram illustrating an example substrate processing sequence and the resulting dishing of the substrate.

FIG. 2 is a schematically illustrated block diagram illustrating an example substrate processing and repair process, according to an embodiment.

FIG. 3 is a schematically illustrated block diagram illustrating an example substrate processing and repair process, according to a second embodiment.

FIG. 4 is a schematically illustrated block diagram illustrating an example substrate processing and repair process, according to a third embodiment.

SUMMARY

Various embodiments of methods and techniques for repairing processed semiconductor substrates, and associated devices, are disclosed. The embodiments comprise methods to remedy the erosion or “dishing” resulting from chemical mechanical polishing/planarizing (CMP) of the substrates, and particularly at locations where there is a higher density of metallic structures embedded within the substrates. In some embodiments, unique formularies are used to carry out the described methods and techniques.

In various implementations, the substrate has a barrier layer disposed in one or more cavities of the substrate and a conductive material disposed in the one or more cavities, forming one or more conductive interconnect structures. An example process includes dry etching the surface of the substrate, including the barrier layer, until a preselected portion of the conductive material protrudes from the cavities above the surface of the substrate. In some embodiments, a first selective etchant (a wet etchant) may also be applied to etch the surface of the substrate, forming a smooth flat surface, without damaging the metallic interconnect structures.

The example process includes selectively wet etching the conductive material protruding from the cavities, including applying a second selective etchant to the conductive material for a preselected period of time or until an end point of the conductive material has a preselected height relative to the surface of the substrate. In some implementations, the process includes selectively wet etching the conductive material until the end point of the conductive material is approximately level with the surface of the substrate or recessed a preselected amount within the one or more cavities below the surface of the substrate. In various embodiments, the second selective etchant is formulated to remove the conductive material, without roughening the smooth surface of the substrate.

In an implementation, the process includes building up the “dished” surface of the substrate by filling the defects with a dielectric material and coating the surface of the substrate with a layer of the dielectric material to form a planarizing layer. In another implementation, the process includes leaving at least a portion of the barrier layer intact during dry etching, applying a dielectric material to the barrier layer to form a planarizing layer, and dry etching the planarizing layer and the at least a portion of the barrier layer until the end point of the conductive material has the preselected height relative to the surface of the substrate.

In some implementations, the dry etching is performed using a high selectivity copper slurry, leaving at least a portion of the barrier layer intact, and dry etching at least a portion of the barrier layer and the surface of the substrate until the end point of the conductive material has the preselected height relative to the surface of the substrate.

In an example implementation, the first selective etchant comprises a source of fluoride ions, one or more organic acids, glycerol, and a complexing agent, where a content of the source of fluoride ions is less than 2% of the formulary, a content of the one or more organic acids is less than 2% of the formulary, and a content of the glycerol is less than 10% of the formulary. In another example implementation, the second selective etchant comprises one or more oxidizing agents, one or more organic acids, and glycerol, where the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary.

In an alternate implementation, the first selective etchant and the second selective etchant include a common formulary. In the implementation, combining the common formulary with one or more additives at preselected process stages allows for the etching of dielectric (e.g., the first selective etchant) or the etching of metals (e.g., the second selective etchant) as appropriate for the process stage.

Various implementations and arrangements are discussed with reference to electrical and electronics components and varied carriers. While specific components (i.e., wafers, integrated circuit (IC) chip dies, etc.) are mentioned, this is not intended to be limiting, and is for ease of discussion and illustrative convenience. The techniques and devices discussed with reference to a wafer, die, or the like, are applicable to any type or number of electrical components, circuits (e.g., integrated circuits (IC), mixed circuits, ASICS, memory devices, processors, etc.), groups of components, packaged components, structures (e.g., wafers, panels, boards, PCBs, etc.), and the like, that may be coupled to interface with each other, with external circuits, systems, carriers, and the like. Each of these different components, circuits, groups, packages, structures, and the like, can be generically referred to as a “microelectronic element.” For simplicity, such components will also be referred to herein as a “die” or a “substrate.”

The disclosed processes are illustrated using block flow diagrams. The order in which the disclosed processes are described is not intended to be construed as a limitation, and any number of the described process blocks can be combined in any order to implement the processes, or alternate processes. Additionally, individual blocks may be deleted from the processes without departing from the spirit and scope of the subject matter described herein. Furthermore, the disclosed processes can be implemented in any suitable manufacturing or processing apparatus or system, along with any hardware, software, firmware, or a combination thereof, without departing from the scope of the subject matter described herein.

Implementations are explained in more detail below using a plurality of examples. Although various implementations and examples are discussed here and below, further implementations and examples may be possible by combining the features and elements of individual implementations and examples.

DETAILED DESCRIPTION Overview

A schematically illustrated block diagram 100 is shown at FIG. 1, illustrating an example substrate processing sequence and the resulting dishing 112 of the substrate 102. A substrate 102 may include wafers, such as GaAs, diamond coated substrates, silicon carbide, silicon wafers, flat panels, glasses, ceramics, circuit boards, packages, an interposer, structures with or without an embedded device or devices, etc. For clarity, the substrate 102 comprises a surface of interest processed for intimate contact with another surface.

As shown in FIG. 1 at block (A), a semiconductor substrate 102 is coupled to a carrier 104. The carrier 104 may comprise a semiconductor device, a backend of the line routing layer, an RDL layer or typically a wiring structure. Cavities or trenches are formed in the substrate 102 for forming conductive interconnect structures 106, or the like. The said cavities may be a blind cavity in which the bottom surface of the cavities contacts the wiring features beneath. In some applications, the cavities are etched in a dielectric material with or without wiring features beneath the cavity. A barrier metal layer 108 is applied to the substrate 102 surface, to prevent diffusion into the semiconductor substrate 102. A damascene process may be used to fill the cavities in the substrate 102 with a conductive material (such as copper, for example), to form the interconnect structures 106, vias, trenches, combinations of vias and trenches, or the like. The metal filling step process commonly leaves an overfill 110 of the conductive material on the surface of the substrate 102 and barrier layer 108.

As shown at block (B), the conductive overfill 110 is removed (here, to the barrier layer 108), by chemical mechanical polishing (CMP), for example. At block (C), the CMP process is further used to remove the metallic barrier layer 108. As shown at block (C), CMP polishing the substrate 102 can result in dielectric erosion and dishing 112 at the location of the interconnect structures 106. For example, depending on the polishing variables, the erosion 112 may be greater than 20 nm in depth for damascene cavities less than 1 micron in depth.

The illustrations at blocks (D), (E), and (F) show examples of substrate bonding using a direct bond interconnect (DBI) technique, i.e. directly bonding the surfaces of the semiconductor substrates without an adhesive and directly connecting the interconnect structures without an intervening reflowable material, such as solder. For example, the DBI technique may use pressure and/or heat to bond the substrates (102, 114) and the interconnects (106, 116). The illustration at block (D) shows bonding between a substrate with erosion (102) bonded to a substrate without erosion (114). In this example, a gap exists between the substrates 102 and 114 at the location of the interconnects 106 and 116. The gap is a result of excessive dielectric erosion and dishing from the polishing step describe earlier. The gap can result in poor bonding between the substrates 102 and 114, as well as poor bonding and discontinuity between the interconnects 106 and 116. As shown at block (E), the gap can be larger when both substrates 102 and 114 have excessive erosion at the location of the interconnects 106 and 116, respectively. The diagram at block (F) shows an ideal scenario, where the substrates 102 and 114 have minimal or no erosion of the dielectric and minimal dishing, and no gap is present. As shown at block (F), there is intimate contact between the surfaces of substrates 102 and 114, and the interconnect features 106 and 116 are connected without obvious void defects.

Example Embodiments

FIG. 2 is a schematically illustrated block diagram illustrating an example substrate processing and repair process 200, according to an embodiment. As described with reference to FIG. 1, processing of a substrate 102, including removal of the overfill 110 and the metallic barrier 108 can result in a recess 112, or erosion of the substrate 102 at the location of the interconnects 106. This is also illustrated in FIG. 2, at block (A) and block (B). Rather than discard the substrate 102 because of the defects, the defective substrate 102 may be repaired or recovered by the corrective methods disclosed herein.

Referring to FIG. 2, at block (C), the eroded surface of the substrate 102 (including the recess 112) is built up to re-surface. In one example, a dielectric (such as a thin oxide layer, a glass, or the like) can be coated onto (e.g., spin-on, etc.) the surface of the substrate 102, filling the recess 112 and forming a dielectric planarizing layer 202 over the eroded surface of the substrate 102. In some examples, the planarizing layer 202 may be less than 200 nm thick, or as needed to form a planar surface.

In an embodiment, the dielectric layer 202 may be partially polished to further smooth the coated dielectric layer 202. In an alternate embodiment, a first wet selective etchant (or dielectric etchant) may be used to selectively etch the dielectric layer 202 and the substrate dielectric 102 without roughening the metallic interconnects 106, or the new surface of the etched substrate 102. In the embodiment, the first selective etchant does not substantially affect the surface of the substrate 102, particularly the flatness/smoothness (nano-scale topography) of the surface.

In an implementation, the first selective etchant comprises glycerated diluted hydrofluoric acid or buffered hydrofluoric acid, organic acid, and deionized water, with or without a stabilizing additive. In some formulary, a first selective etchant for the dielectric 102 may comprise an inorganic or organic acid containing a fluoride ion. It is preferable that the content of the fluoride ion be less 2% and preferably less than 0.5% and preferably less than 0.1%. Examples of the sources of fluoride ions may include hydrofluoric acid, buffered oxide etch, or tetrabutylammonium fluoride. The first selective etchant solution may also comprise aliphatic or non-aliphatic organic acids, and more than one organic acid may be used in the formulary. The organic acid content of the first selective etchant may typically be less than 2% and preferably less than 1%. Examples of organic acid may include formic acid, acetic acid, methyl sulfonic acid and their likes. In some embodiments, mineral acids (for example, a very small amount of sulfuric acid) may be used. However, the amount used should not roughen the surface of the etched metallic interconnect.

In various embodiments, glycerol is incorporated into the first selective etchant. The content of glycerol may vary between 0.5 to 25% of the formulary, and preferably under 10%. In other applications, a very small amount of amide, amines, butylated hydroxyanisole (BHA), butylated hydroxytoulene, or organic carbonates may be added to the formulary. It is preferable that the total content of these additional additives be less than 5% and preferably less than 1%. It is also desirable that a complexing agent that suppresses the removal or etching or roughening of the surface of the metallic interconnect 106 be incorporated into the formulary. In the case of copper a suitable copper complexing agent with one or more triazole moieties may be used. The concentration of the complexing agent is should less than 2%, and preferably less than 1%, 0.2% and less than 200 ppm in some instances.

At block (D), the dielectric planarizing layer 202 and a portion of the substrate 102 (and any residual barrier layer 108 present) are dry etched, using the exposed ends 204 of the interconnects 106 as an indicator of a stopping point. This forms a planar surface on the substrate 102, with the interconnects 106 protruding a preselected distance above the surface of the substrate 102. Alternatively, at block (D), the dielectric layer 202 and a portion of the substrate 102 layer are removed by wet etchant, such as the first selective etchant for example, using the exposed ends 204 of the interconnects 106 as an indicator of a stopping point. This forms a planar surface on the substrate 102, with the interconnects 106 protruding a preset distance from the surface of the substrate 102. In an embodiment, the removal of dielectric layer 202 material is a function of time, that is, the longer the first selective etchant is allowed to contact the dielectric layer 202, the more dielectric material is removed. Accordingly, the first selective etchant is applied for a specified period of time.

At block (E), the process includes selectively wet etching the metallic interconnects 106, without roughing the surface of the interconnects 106 and without roughing the dielectric layer 202 (if a portion is still present) or the surface of the substrate 102. In an embodiment, a second selective etchant is used for this step in the process. The second selective etchant is applied to the conductive material of the interconnect structures 106, and removes the desired material of the interconnects 106 while maintaining a low surface roughness of the substrate 102.

For example, in the embodiment, the second selective etchant does not substantially affect the surface of the substrate 102, particularly the flatness/smoothness (nano-scale topography) of the surface. In one embodiment, the removal of metallic interconnect material is a function of time, that is, the longer the second selective etchant is allowed to contact the metal of the interconnects 106, the more metal of the interconnects 106 is removed. Accordingly, the second selective etchant may be applied for a specified period of time. In another embodiment, the second selective etchant is applied to the conductive material until the exposed end points 204 of the conductive material interconnects 106 have a preselected height relative to the surface of the substrate 102. For instance, the second selective etchant may be applied to the conductive material of the interconnects 106 until the exposed end points 204 of the interconnects 106 are approximately level with the surface of the substrate 102 or are recessed a preselected amount below the surface of the substrate 102.

In one implementation, the second selective etchant comprises a composition that removes, for example, the interconnect 106 metal (in the case of copper or copper oxide) at a controlled rate. The removal is such that the roughness (and lack of roughness) of the copper remains practically unchanged after the removal step. In one embodiment, after the metal removal step, the roughness of the metallic interconnect 106 is less than 2 nm, and in other cases, the roughness is less 0.5 nm. One unique attribute of the formulary of the second selective etchant is that the roughness of the etched metal layer is independent of the duration of the etch. In one embodiment, the second selective etchant may be used as slurry in the finishing step of the CMP process.

In an implementation, the second selective etchant comprises a glycerated diluted oxidizing agent, organic acid, and deionized water, with or without a stabilizing additive. In an example, a formulary of the second selective etchant for the metallic interconnects 106 may comprise an inorganic or organic peroxide, typically less than 2% and preferably less than 0.5%. An example of the oxidizing agent may include hydrogen peroxide and urea peroxide. One or more oxidizing agents may be used in the formulary for the second selective etchant. The organic acid may comprise aliphatic or non-aliphatic organic acids, and also more than one organic acid may be used in the formulary. The organic acid content of the second selective etchant may typically be less than 2% and preferably less than 1%. Examples of the organic acid may include formic acid, acetic acid, methyl sulfonic acid, and their likes. In some embodiments, mineral acids (for example, a very small amount of sulfuric acid) may be used, however, the amount should not roughen the surface of the etched metallic interconnect 106. In one embodiment, glycerol is incorporated in the second selective etchant, where the content of glycerol may vary between 0.5 to 25% of the formulary, and preferably under 10%. In other applications a very small amount of amide, amines, butylated hydroxyanisole (BHA), butylated hydroxytoulene, or organic carbonates may be added to the formulary. It is preferable that the total content of these additional additives be less than 5% and preferably less than 1%.

As illustrated at block (F), polishing with the second selective etchant can be performed until the surfaces of the end points 204 of the interconnects 106 are at or slightly below (less than 8 nm, for example) the surface of the substrate 102, to allow for the metal (e.g., copper) of the interconnects 106 to expand during bonding. The resulting substrate 102 is substantially free from erosion, and the topography of the substrate 102 surface is more flat/smooth (e.g., at or below 1 nm rms) than using CMP processing alone, making the surface of the substrate 102 ideal for bonding.

FIG. 3 is a schematically illustrated block diagram illustrating an example substrate processing and repair sequence 300, according to a second embodiment. As shown at block (A), the substrate 102 is prepared in a damascene process as described with reference to FIGS. 1 and 2. At block (B), the overfill 110 is removed by CMP process, for example, leaving the metallic barrier layer 108. In an embodiment, the metallic barrier 108 comprises a tantalum or titanium or tungsten-based material, or the like.

As shown at block (C), a thin planarizing dielectric layer 302 is added to the surface of the barrier layer 108. In an example, the planarizing dielectric layer 302 is less than 200 nm thick, or as desired. In an embodiment, using the planarizing layer 302 with the barrier layer 108 can reduce the dishing effect on the surface of the substrate 102.

As shown at block (D), the planarizing dielectric layer 302 and the barrier layer 108 are removed using a dry etch process, for example, using the end points 204 of the interconnects 106 as an indicator of a stopping point. This forms a planar surface on the substrate 102, with the ends 204 of the exposed interconnects 106 protruding a preset distance from the surface of the substrate 102.

At block (E), the process includes selectively wet etching the metallic interconnects 106, without roughing the surface of the interconnects 106 or roughing the dielectric layer 302 (if it is still present) or the surface of the substrate 102 (as described above). In an embodiment, the second selective etchant (as described with reference to FIG. 2) is used for this step in the process. The second selective etchant removes the desired material of the interconnects 106 while maintaining a low surface roughness of the substrate 102.

As illustrated at block (F), polishing with the second selective etchant can be performed until the surfaces of the ends 204 of the interconnects 106 are at or slightly below (less than 8 nm, for example) the surface of the substrate 102. The resulting substrate 102 is substantially free from erosion, with a smooth surface topography, making the surface of the substrate 102 ideal for bonding.

FIG. 4 is a schematically illustrated block diagram illustrating an example substrate processing and repair sequence 400, according to a third embodiment. As shown at block (A), the substrate 102 is prepared in a damascene process as described with reference to FIGS. 1, 2, and 3. At block (B), the overfill 110 is removed by CMP process, for example, leaving the metallic barrier layer 108. In an example, a high selectivity copper slurry (e.g., greater than 10) is used with the copper barrier 108.

As shown at block (C), the barrier layer 108 is removed using a dry etch process, for example, using the ends 204 of the interconnects 106 as an indicator of a stopping point. This forms a planar surface on the substrate 102, with the exposed ends 204 of the interconnects 106 protruding a preset distance from the surface of the substrate 102.

At block (D), the process includes selectively wet etching the metallic interconnects 106, without roughing the surface of the interconnects 106 or roughing the dielectric layer 202, 302 (if present) or the surface of the substrate 102. In an embodiment, the second selective etchant (as described with reference to FIGS. 2 and 3) is used for this step in the process. The second selective etchant removes the desired material of the interconnects 106 while maintaining a low surface roughness of the substrate 102. In an implementation, the process provides an etching uniformity of less than 2 nm.

In alternate implementations, other techniques may be included in the processes disclosed in various combinations, and remain within the scope of the disclosure.

Conclusion

Although the implementations of the disclosure have been described in language specific to structural features and/or methodological acts, it is to be understood that the implementations are not necessarily limited to the specific features or acts described. Rather, the specific features and acts are disclosed as representative forms of implementing example devices and techniques.

Each claim of this document constitutes a separate embodiment, and embodiments that combine different claims and/or different embodiments are within the scope of the disclosure and will be apparent to those of ordinary skill in the art upon reviewing this disclosure. 

What is claimed is:
 1. A method of repairing defects on a surface of a substrate, the substrate having a barrier layer disposed in one or more cavities of the substrate and a conductive material disposed in the one or more cavities, the method comprising: dry etching the surface of the substrate, including the barrier layer, until a preselected portion of the conductive material protrudes from the cavities above the surface of the substrate; and selectively wet etching the conductive material protruding from the cavities, including applying a selective etchant to the conductive material for a preselected period of time or until an end point of the conductive material has a preselected height relative to the surface of the substrate.
 2. The method of claim 1, wherein the selective etchant is a second selective etchant; and further comprising selectively wet etching the surface of the substrate using a first selective etchant until a preselected portion of the conductive material protrudes from the cavities above the surface of the substrate.
 3. The method of claim 2, wherein the first selective etchant comprises: glycerated diluted hydrofluoric acid or buffered hydrofluoric acid, organic acid, and deionized water, with or without a stabilizing additive.
 4. The method of claim 2, wherein the first selective etchant comprises one or more triazole moieties, wherein the content of the complexing agent is less than 2% of the formulary.
 5. The method of claim 2, wherein the first selective etchant is formulated with a complexing agent to selectively etch the surface of the substrate without roughening a surface of the conductive material.
 6. The method of claim 5, wherein the complexing agent comprises: an inorganic or organic acid containing a fluoride ion, wherein the content of the fluoride ion is less than 2% of the formulary.
 7. The method of claim 1, further comprising building up the surface of the substrate by filling the defects with a dielectric material and coating the surface of the substrate with a layer of the dielectric material to form a planarizing layer.
 8. The method of claim 7, further comprising polishing the planarizing layer and the surface of the substrate to form a planar bonding surface.
 9. The method of claim 7, further comprising removing at least a portion of the planarizing layer and at least a portion of the substrate until a preselected portion of the conductive material protrudes from the cavities above the surface of the substrate.
 10. The method of claim 1, further comprising leaving at least a portion of the barrier layer intact during dry etching; applying a dielectric material to the barrier layer to form a planarizing layer; and dry etching the planarizing layer and the at least a portion of the barrier layer until the end point of the conductive material has the preselected height relative to the surface of the substrate.
 11. The method of claim 1, wherein the dry etching is performed using a high selectivity copper slurry, leaving at least a portion of the barrier layer intact; and further comprising dry etching the at least a portion of the barrier layer and the surface of the substrate until the end point of the conductive material has the preselected height relative to the surface of the substrate.
 12. The method of claim 1, further comprising selectively wet etching the conductive material using the selective etchant until the end point of the conductive material is approximately level with the surface of the substrate or recessed a preselected amount within the one or more cavities below the surface of the substrate.
 13. The method of claim 1, wherein the selective etchant comprises: one or more oxidizing agents, one or more organic acids, and glycerol, wherein the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary.
 14. A formulary for selectively etching a metal without roughening a surface of said metal, the formulary comprising: one or more oxidizing agents; one or more organic acids; and glycerol, wherein the one or more oxidizing agents and the one or more organic acids are each less than 2% of formulary and the glycerol is less than 10% of the formulary.
 15. The formulary of claim 14, wherein the formulary further comprises a stabilizing agent.
 16. The formulary of claim 14, wherein the oxidizing agent comprises an inorganic peroxide or an organic peroxide or a combination of an inorganic peroxide and an organic peroxide.
 17. The formulary of claim 14, wherein the oxidizing agent comprises hydrogen peroxide or urea peroxide or a combination of hydrogen peroxide and urea peroxide.
 18. The formulary of claim 14, wherein the organic acid comprises acetic acid, formic acid, or methylsulfonic acid, or a combination thereof.
 19. A formulary for selectively etching a dielectric oxide layer without roughening a surface of said dielectric oxide layer or roughening a surface of a metal layer, the formulary comprising: a source of fluoride ions; one or more organic acids; glycerol; and a complexing agent, wherein a content of the source of fluoride ions is less than 2% of the formulary, a content of the one or more organic acids is less than 2% of the formulary, and a content of the glycerol is less than 10% of the formulary.
 20. The formulary of claim 19, wherein the complexing agent comprises one or more triazole moiety and a content of the complexing agent is less than 1% of the formulary. 